Choosing SIMM's for use with the Acorn Risc PC

Number:       259
Issue:        0.04
Author:       Dean Murphy
Date:         20th April 1994
Last updated: 16th May 1995
HTML Author:  Dean Murphy

Applicable Hardware: Acorn Risc PC

Related Application Notes: NONE

Every effort has been made to ensure that the information in this document is true and correct at the time of printing. However, the products described in this document are subject to continuous development and improvements and Acorn Computers Limited reserves the right to change its specifications at any time. Acorn Computers Limited cannot accept liability for any loss or damage arising from the use of any information or particulars in this leaflet. Acorn, the Acorn Logo, Acorn Risc PC, ECONET, AUN, Pocket Book and ARCHIMEDES are trademarks of Acorn Computers Limited.

ARM is a trademark of Advance RISC Machines Limited.
All other trademarks acknowledged.
©1994 Acorn Computers Limited. All rights reserved.

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Introduction

This document has been written as a technical specification to help purchasers of SIMMs for the Risc PC ensure that the correct devices are used. The document is by it's very nature quite technical, this cannot be avoided.

The Acorn Risc PC is the first of Acorn's ARM based RISC OS platforms to allow SIMMS (Single-In-Line Memory Modules) to be fitted to support DRAM (Dynamic Random Access Memory). Two SIMM banks are catered for, and any combination of 32bit SIMMs is possible with either of the SIMM sockets left empty. The operating system does however expect at least 2 MBytes of DRAM to be available.

Overview

The SIMM must have a 72 pin connector with 32 bit data (36 bit DRAM devices will NOT work).
It must not have more than 16 devices (DRAM chips) on board.
Devices must be 70ns (or faster).
Devices must be Square Array (Described later in this document).
Devices must support 'fast paged mode' and CAS before RAS.

Memory Sizes

       2 MBytes (512K  * 32bits)
       4 MBytes (  1M  * 32bits)
       8 MBytes (  2M  * 32bits)
      16 MBytes (  4M  * 32bits)
      32 MBytes (  8M  * 32bits)
      64 MBytes ( 16M  * 32bits)   When available
     128 MBytes ( 32M  * 32bits)   When available

Either or both SIMM sockets may be used, with any mix of sizes provided a minimum of 2MBytes is fitted.

NOTE: The Risc PC was designed to take up to two SIMMS. Acorn do not recommend the use of more than two SIMMS with this machine. There are currently no plans to release a Risc PC which has both SIMM sockets populated.

Detailed Specifications

There are a number of other specifications that are required, although many SIMMs meet them:

The maximum physical size is 108mm long, 36.2mm wide and 9.4mm thick.
The DRAM must use the same number of bits for both row and column address (square array) ie.
```
         Ra<8:0> for 2 MByte
         Ra<9:0> for 4 or 8 MByte
         Ra<10:0> for 16 or 32 MByte.
```
There are a few 16 MByte and 32 MByte SIMMs that use Ra<11:0> for the row address and Ra<9:0> for the column address. Although these parts are sometimes sold for use with Apple equipment, they are non-standard, and are unsuitable for use with the Acorn Risc PC as they will appear to the computer as a 4 or 8 Mbytes.
As a guide the Hitachi 16 & 32 MByte SIMMs use 5117400 parts which are correct. Some makes of 16/32 MByte SIMM use unsuitable 5116400 parts.
Another way of differentiating between the two types of SIMM is the number of refresh cycles required. The correct parts used in the 16 & 32 MByte SIMMs require 2048 refresh cycles, where as the incompatible parts (with an additional address line Ra<11:0>) require 4096 refresh cycles.
Acorn do not recommend the use of SIMMs that are made from more than 16 memory devices (eg 8 on each side) as they are likely to exceed the maximum load specification:
```
           Address      128pF
           WE           140pF
           CAS or RAS   59pF
           Data bus     29pF
```
Older 'composite' SIMMs that are made from more than 16 devices should be avoided.
The DRAM devices used on the SIMM must support 'fast page mode' and 'CAS before RAS' refresh
The 4 ID bits on pin 67, 68, 69 & 70 are not used, and so may be in any state on the SIMM. However, non-standard SIMMs with 5 (or more) ID bits should not be used. (eg Samsung 32 MByte KMM5328100)